ECPi Camera RGB888

Digital Video Port (DVP) is a very simple, low cost, license free protocol for transmitting. images using parallel, low frequency single ended wires. The problem is that there are no DVP Cameras with a 24 bit wide data path, so only smaller, low resolution images are currently possible. One would have to use the more complex, higher frequency, proprietary MIPI CSI, but there are no open source FPGAs with MIPI CSI hard cores currently available. The Lattice Crosslink NX 17/40 is back ordered for two years. The Appicula project to support Gowin FPGAs with MIPI CSI hard cores just started and will take time to complete. There are closed source FPGAs with MIPI CSI, but they are all more expensive. And even if you did find a MIPI CSI FPGA, you would still need a microcontroller to set all of the registers in the inmage sensor. Best to use the ECPi Camera RGB888 application.

This is a reasonably simple application. On the newer (Bookworm and later) releases of the Raspberry Pi OS, you have to edit /boot/firmware/config.txt and add the following lines:

# Configure the GPU to output RGB888
dtparam=rgb888

# Set the device tree overlay sending the gpu output to the 28 pins. 
dtoverlay=vc4-kms-v3d

# Set the timings for the video display. 
dpi_timings=640 0 16 96 48 480 0 11 2 32 0 0 0 60 0 25175000 1

#The fields in order:
#h_active    = 640
#h_sync_pol  = 0      (negative)
#h_fp        = 16     (front porch)
#h_sync      = 96
#h_bp        = 48     (back porch)
#v_active    = 480
#v_sync_pol  = 0      (negative)
#v_fp        = 11
#v_sync      = 2
#v_bp        = 32
#v_offset_a  = 0
#v_offset_b  = 0
#pixel_rep   = 0
#frame_rate  = 60
i#nterlaced  = 0
#pixel_freq  = 25175000   (25.175 MHz)
#aspect      = 1      (4:3)

These values have not yet been tested.

You also have to configure the FPGA. The signal path between the RPi Zero and the FPGA is 28 bits wide. 24 bits of RGB data plus Horizontal Sync, Vertical Sync, Blank and clock. All but the clock are registered and then sent to a dummy module where you can add your logic, and from there, the signal is sent to the GPDI/HDMI/DVI output port. The clock is handled differently. It is sent to the PLL and then through the clock tree network, such that its output is aligned with the input clock, placing both the RPi Zero DPI output and the FPGA fabric in the same clock domain.